?20 10 fairchild semiconductor corporation huf75321d3s t rev. c huf75321d 3st 20a, 55v, 0.036 ohm, n-channel ultrafet power mosfets these n-channel power mosfets are manufactured using the innovative ultrafet? process. this advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. this device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. it was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low- voltage bus switches, and power management in portable and battery-operated products. formerly developmental type ta75321. features 20a, 55v simulation models - temperature compensating pspice? and saber? models - thermal impedance spice and saber models available on the web at: www.fairchildsemi.com peak current vs pulse width curve uis rating curve related literature - tb334, ?guidelines for soldering surface mount components to pc boards? symbol packaging jedec to-252aa product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html for severe environm ents, see our automotive hufa series. all fairchild semiconductor products are manufactured, assembled and tested under iso9000 and qs9000 quality systems certif ication. d g s gate source drain (flange) data sheet nove mber 20 10
?20 10 fairchild semiconductor corporation HUF75321D3ST rev. c absolute maximum ratings t c = 25 o c, unless otherwise specified units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . v dss 55 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . v dgr 55 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v drain current continuous (figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 20 figure 4 a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as figures 6, 14, 15 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 0.625 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . .t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. t j = 25 o c to 150 o c. electrical specifications t c = 25 o c, unless otherwise specified parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 11) 55 - - v zero gate voltage drain current i dss v ds = 50v, v gs = 0v - - 1 a v ds = 45v, v gs = 0v, t c = 150 o c--2 5 0 a gate to source leakage current i gss v gs = 20v - - 100 na on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 10) 2 - 4 v drain to source on resistance r ds(on) i d = 20a, v gs = 10v (figure 9) - 0.030 0.036 ? thermal specifications thermal resistance junction to case r jc (figure 3) - - 1.6 o c/w thermal resistance junction to ambient r ja to-251, to-252 - - 100 o c/w switching specifications (v gs = 10v) turn-on time t on v dd = 30v, i d ? 20a, r l = 1.5 ? , v gs = 10v, r gs = 25 ? --100ns turn-on delay time t d(on) -11- ns rise time t r -55- ns turn-off delay time t d(off) -47- ns fall time t f -66- ns turn-off time t off --170ns gate charge specifications total gate charge q g(tot) v gs = 0v to 20v v dd = 30v, i d ? 20a, r l = 1.5 ? i g(ref) = 1.0ma (figure 13) -3644nc gate charge at 10v q g(10) v gs = 0v to 10v - 21 26 nc threshold gate charge q g(th) v gs = 0v to 2v - 1.3 1.6 nc gate to source gate charge q gs -3-nc reverse transfer capacitance q gd -9-nc HUF75321D3ST
?20 10 fairchild semiconductor corporation HUF75321D3ST rev. c capacitance specifications input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 12) - 680 - pf output capacitance c oss - 270 - pf reverse transfer capacitance c rss -60- pf electrical specifications t c = 25 o c, unless otherwise specified parameter symbol test conditions min typ max units source to drain diode specifications parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 20a - - 1.25 v reverse recovery time t rr i sd = 20a, di sd /dt = 100a/ s--5 9n s reverse recovered charge q rr i sd = 20a, di sd /dt = 100a/ s--8 2n c typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum cont inuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 175 15 5 0 25 50 75 100 125 150 10 20 i d , drain current (a) t c , case temperature ( o c) 25 17 5 t, rectangular pulse duration (s) single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -5 0.1 0.01 z jc , normalized thermal impedance 1 2 HUF75321D3ST
?20 10 fairchild semiconductor corporation HUF75321D3ST rev. c figure 4. peak current capab ility figure 5. forward bias safe operating area note: refer to fairchild application notes an9321 and an 9322. figure 6. unclamped inductive switching capability figure 7. saturation characteristics figure 8. transfer characteristics typical performance curves (continued) 10 1 10 0 10 -1 10 -2 10 -3 10 -4 10 -5 10 100 500 t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: v gs = 10v i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region v gs = 20v 10 100 300 10 100 1 12 0 0 v ds , drain to source voltage (v) i d , drain current (a) t j = max rated t c = 25 o c 100 s 10ms 1ms limited by r ds(on) area may be operation in this v dss(max) = 55v 0.1 0.01 10 i as , avalanche current (a) t av , time in avalanche (ms) t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] starting t j = 25 o c starting t j = 150 o c 1 300 1 10 100 03 . 0 4 . 57 . 5 i d , drain current (a) v ds , drain to source voltage (v) v gs = 5v 0 15 30 75 6.0 1.5 60 45 v gs = 6v v gs = 10v v gs = 20v v gs = 8v v gs = 7v t c = 25 o c pulse duration = 80 s duty cycle = 0.5% max 03 . 0 4 . 5 6 . 0 7 . 5 1.5 0 15 30 i d , drain current (a) v gs , gate to source voltage (v) 25 o c pulse duration = 80 s duty cycle = 0.5% max v dd = 15v 75 45 60 -55 o c 175 o c HUF75321D3ST
?20 10 fairchild semiconductor corporation HUF75321D3ST rev. c figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature figure 11. normalized drain to source breakdown voltage vs junction temperature figure 12. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an 7260. figure 13. gate charge waveforms for constant gate current typical performance curves (continued) 1.0 1.5 2.0 2.5 -40 0 40 80 120 160 200 0.5 -80 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 20a pulse duration = 80 s duty cycle = 0.5% max 0.8 1.0 1.2 -40 0 40 80 120 160 200 0.6 -80 normalized gate t j , junction temperature ( o c) threshold voltage v gs = v ds , i d = 250 a 0.9 1.0 1.1 1.2 -40 0 40 80 120 160 200 -80 t j , junction temperature ( o c) normalized drain to source i d = 250 a breakdown voltage 800 400 0 0 1020304050 c, capacitance (pf) 600 v ds , drain to source voltage (v) 200 c iss c oss c rss 60 1000 v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd 10 8 6 4 0 v gs , gate to source voltage (v) v dd = 30v 2 15 20 0 q g , gate charge (nc) 51 0 i d = 20a i d = 10a i d = 5a waveforms in descending order: 25 HUF75321D3ST
?20 10 fairchild semiconductor corporation HUF75321D3ST rev. c test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms figure 16. gate charge test circuit figure 17. gate charge waveform figure 18. switching time test circuit figure 19. resistive switching waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) v gs = 10v q g(tot) v gs = 20 v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 HUF75321D3ST
?20 10 fairchild semiconductor corporation HUF75321D3ST rev. c pspice electrical model .subckt huf75321d 2 1 3 ; rev 4/29/98 ca 12 8 9.96e-10 cb 15 14 9.83e-10 cin 6 8 6.18e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 59.54 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 3.57e-9 lsource 3 7 4.25e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 5.50e-3 rgate 9 20 2.25 rldrain 2 5 10 rlgate 1 9 35.7 rlsource 3 7 42.5 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rso urcemod 16.30e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51) /abs(v (5,5 1)))*(pwr(v (5,5 1)/(1e -6*101),2.5))} .model dbodymod d (is = 7.47e-13 rs = 6.45e-3 trs1 = 2.01e-3 trs2 = 1.21e-6 cjo = 1.02e-9 tt = 3.21e-8 m = 0.50) .model dbreakmod d (rs = 2.01e- 1trs1 = 3.62e- 3trs2 = 6.01e-7) .model dplcapmod d (cjo = 9.0e-1 0is = 1e-3 0n = 10 m = 0.85) .model mmedmod nmos (vto = 3.25 kp = 1.75 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 2.25) .model mstromod nmos (vto = 3.65 kp = 32.00 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 2.91 kp = 0.07 is = 1e- 30 n = 10 tox = 1 l = 1u w = 1u rg = 22.5 rs = 0.1) .model rbreakmod res (tc1 = 1.05e- 3tc2 = 1.21e-7) .model rdrainmod res (tc1 = 2.40e-2 tc2 = 1.02e-6) .model rslcmod res (tc1 = 2.07e-4 tc2 = 4.67e-5) .model rsourcemod res (tc1 = 0 tc2 =0) .model rvthresmod res (tc = -3.01e-3 tc2 = -8.85e-6) .model rvtempmod res (tc1 = -1.96e- 3tc2 = 1.39e-6) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -7.85 voff= -4.85) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -4.85 voff= -7.85) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 0.00 voff= 3.00) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 3.00 voff= 0.00) .ends note: for further discussion of the pspice m odel, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1 991, written by william j. hepp and c. frank w heatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 HUF75321D3ST
?20 10 fairchild semiconductor corporation HUF75321D3ST rev. c saber electrical model rev april 1998 template huf75321d n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 7.47e-13, cjo = 1.02e-9, tt = 3.21e-8, m = 0.5) d..model dbreakmod = () d..model dplcapmod = (cjo = 9e-10, is = 1e-30, n = 10, m = 0.85) m..model mmedmod = (type=_n, vto = 3.25, kp = 1.75, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.65, kp = 32, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.91, kp = 0.07, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.85, voff = -4.85) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4.85, voff = -7.85) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 3.0) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 3.0, voff = 0) c.ca n12 n8 = 9.96e-10 c.cb n15 n14 = 9.83e-10 c.cin n6 n8 = 6.18e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 =3.57e-9 l.lsource n3 n7 = 4.25e-9 m.mmed n16 n6 n8 n8 = model=mmedm od, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mst rongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 1.21e-7 res.rdbody n71 n5 = 6.45e-3, tc1 = 2.01e-3, tc2 = 1.21e-6 res.rdbreak n72 n5 = 2.01e-1, tc1 = 3.62e-3, tc2 = 6.01e-7 res.rdrain n50 n16 = 5.5e-3, tc1 = 2.4e-2, tc2 = 1. 02e-6 res.rgate n9 n20 = 2.25 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 35.7 res.rlsource n3 n7 = 42.5 res.rslc1 n5 n51 = 1e-6, tc1 = 2. 07e-4, tc2 = 4.67e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 16.3e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.96e-3, tc2 = 1.39e-6 res.rvthres n22 n8 = 1, tc1 = -3.01e-3, tc2 = -8.85e-6 spe.ebreak n11 n7 n17 n18 = 59.54 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s 1amod sw_vcsp.s1b n 13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n 13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/101))** 2.5)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 l source rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbody rdbreak 72 71 HUF75321D3ST
?20 10 fairchild semiconductor corporation HUF75321D3ST rev. c spice thermal model rev 24 february 1999 huf75321d ctherm1 th 6 2.7e-3 ctherm2 6 5 3.7e-3 ctherm3 5 4 1.2e-2 ctherm4 4 3 3.8e-3 ctherm5 3 2 1.4e-2 ctherm6 2 tl 10.55 rtherm1 th 6 1.10e-2 rtherm2 6 5 2.72e-2 rtherm3 5 4 7.67e-2 rtherm4 4 3 4.30e-1 rtherm5 3 2 6.49e-1 rtherm6 2 tl 8.61e-2 saber thermal model saber thermal model huf75321d template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 2.7e-3 ctherm.ctherm2 6 5 = 3.7e-3 ctherm.ctherm3 5 4 = 1.2e-2 ctherm.ctherm4 4 3 = 3.8-3 ctherm.ctherm5 3 2 = 1.4e-2 ctherm.ctherm6 2 tl = 10.55 rtherm.rtherm1 th 6 = 1.10e-3 rtherm.rtherm2 6 5 = 2.72e-2 rtherm.rtherm3 5 4 = 7.67e-2 rtherm.rtherm4 4 3 = 4.30e-1 rtherm.rtherm5 3 2 = 6.49e-1 rtherm.rtherm6 2 tl = 8.61e-2 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case HUF75321D3ST
? fairchild semiconductor corporation www.fairchildsemi.com trademarks the following includes registered and unregistered trademarks and se rvice marks, owned by fairchild semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. accupower ? auto-spm ? build it now ? coreplus ? corepower ? crossvolt ? ctl ? current transfer logic ? deuxpeed ? dual cool? ecospark ? efficientmax ? esbc ? ? fairchild ? fairchild semiconductor ? fact quiet series ? fact ? fast ? fastvcore ? fetbench ? flashwriter ? * fps ? f-pfs ? frfet ? global power resource sm green fps ? green fps ? e-series ? g max ? gto ? intellimax ? isoplanar ? megabuck ? microcoupler ? microfet ? micropak ? micropak2 ? millerdrive ? motionmax ? motion-spm ? optohit? optologic ? optoplanar ? ? pdp spm? power-spm ? powertrench ? powerxs? programmable active droop ? qfet ? qs ? quiet series ? rapidconfigure ? ? saving our world, 1mw/w/kw at a time? signalwise ? smartmax ? smart start ? spm ? stealth ? superfet ? supersot ? -3 supersot ? -6 supersot ? -8 supremos ? syncfet ? sync-lock? ? * the power franchise ? tinyboost ? tinybuck ? tinycalc ? tinylogic ? tinyopto ? tinypower ? tinypwm ? tinywire ? trifault detect ? truecurrent ? * serdes ? uhc ? ultra frfet ? unifet ? vcx ? visualmax ? xs? * trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical co mponents in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provi ded in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. anti-counterfeiting policy fairchild semiconductor corporation's anti-counterfeiting policy. fairchild's anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support. counterfeiting of semiconductor parts is a growing problem in t he industry. all manufacturers of semiconductor products are exp eriencing counterfeiting of their parts. customers who inadvertently purchase counter feit parts experience many problems such as loss of brand reputation, substandard p erformance, failed applications, and increased cost of production and manufacturing delays. fairchild is taking strong measures to protect ourselves and our cus tomers from the proliferation of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts eit her directly from fairchild or from a uthorized fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or from authorized fairchi ld distributors are genuine parts, have full traceability, meet fairch ild's quality standards for handling and storage and pr ovide access to fair child's full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and will appropr iately address any warranty issues t hat may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from u nauthorized sources. fairchild is committed to combat this glo bal problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. product status definitions definition of terms datasheet identification product status definition advance information formative / in design datasheet contains the design s pecifications for product developmen t. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specific ations. fairchild semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specificati ons on a product that is disconti nued by fairchild semiconductor. the datasheet is for reference information only. rev. i48
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